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Host Interface (HI08)
Table 6-9. Host Status Register (HSR) Bit Definitions (Continued)
Bit Number
4–3
Bit Name
HF[1–0]
Reset Value
0
Host Flags 0, 1
Description
General-purpose flags for host-to-DSP communication. These bits reflect
the status of host flags HF[1–0] in the ICR on the host side. These two
general-purpose flags can be used individually or as encoded pairs in a
simple host-to-DSP communication protocol, implemented in both the
DSP and the host processor software.
2
HCP
0
Host Command Pending
Reflects the status of the CVR[HC] bit. When set, it indicates that a host
command interrupt is pending. HI08 hardware clears HC and HCP when
the DSP core services the interrupt request. If the host clears HC, HCP is
also cleared.
1
HTDE
0
Host Transmit Data Empty
Indicates that the host transmit data register (HTX) is empty and can be
written by the DSP core. HTDE is set when the HTX register is transferred
to the RXH:RXM:RXL registers. The host processor can also set HTDE
using the initialize function. HTDE is cleared when the DSP core writes to
HTX.
0
HRDF
0
Host Receive Data Full
Indicates that the host receive data register (HRX) contains data from the
host processor. HRDF is set when data is transferred from the
TXH:TXM:TXL registers to the HRX register. The host processor can also
clear HRDF using the initialize function.
6.6.3 Host Data Direction Register (HDDR)
The HDDR controls the direction of the data flow for each of the HI08 signals configured as
GPIO. Even when the HI08 functions as the host interface, its unused signals can be configured
as GPIO signals. For information on the HI08 GPIO configuration options, see Section 6.2 , Host
Port Signals , on page 6-3. If Bit DR xx is set, the corresponding HI08 signal is configured as an
output signal. If Bit DR xx is cleared, the corresponding HI08 signal is configured as an input
signal. Hardware and software reset clear the HDDR bits.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DR15 DR14 DR13 DR12 DR11 DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Figure 6-8. Host Data Direction Register (HDDR) (X:$FFFFC8)
DSP56311 User’s Manual, Rev. 2
6-14
Freescale Semiconductor
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